TSMC Plans to Double 16nm Chip Production in Preparation for iPhone 7

The rumor in this article states that the A10 will stay at 16nm like the A9. The improvement due to "3D Transistor stacking" or whatever will be very minimal.

http://wccftech.com/iphone-7-tsmc/

20% expected.

Bit confused, so it's going to be 16nm or 10nm chip?

16nm, 10nm won't be ready for Fall devices.

I'm thinking this years iPhone is just a better 6, rather than a full fledged completely new device.

We have read that the dual camera is still a year away. That the 10nm chip is still a year away. That the new oled displays are still at least a year away. That the iPhone will be the exact same dimensions minus one mm in thickness due to an improved thinner display..
Also note that new 4" iPhone will be in a old case. I would imagine they would have crafted a completely new one unless it wasn't just a kind of placeholder until the next complete iPhone iteration.

I think Apple is working to to get all those things into the iPhone but they are just not quite ready.

This is good news if it takes care of ChipGate.

Let's hope a TSMC chip is guaranteed in all iPhones so as to ensure better battery life.

http://wccftech.com/iphone-7-tsmc/

20% expected.

Oooooh. Neat stuff.

Yeah, a 20% speed jump is what I'd consider minimal. The A9 was nearly twice as fast as the A8 and at least twice as fast as the A7.

The A8 was like up to 30% faster than the A7 I believe.
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I'm thinking this years iPhone is just a better 6, rather than a full fledged completely new device.

We have read that the dual camera is still a year away. That the 10nm chip is still a year away. That the new oled displays are still at least a year away. That the iPhone will be the exact same dimensions minus one mm in thickness due to an improved thinner display..

I think Apple is working to to get all those things into the iPhone but they are just not quite ready.

More like they can't because profit margins.

http://wccftech.com/iphone-7-tsmc/

20% expected.

That's wccftech just repeating the assessment made from Bernstein ('http://blogs.barrons.com/asiastocks/2015/10/22/tsmc-apple-will-pioneer-info-to-build-thinner-phones-bernstein-raises-target/'). Here's the relevant bit:

Compared with the Flip Chip-PoP (Package-on-Package, or simply FC-POP) technology employed currently, InFO removes substrate from package and hence can reduce the thickness of mobile SoC from 1mm to 0.8mm or lower. The shorter distance between logic die and printed circuit board also enables faster thermal dissipation, higher maximal allowable power consumption and possibly 20% better performance (but with power penalty).

In fact, TSMC’s InFO is just one of many variants of fan-out wafer-level package (FOWLP) which has been tried by many but with limited success thus far. With a satisfactory packaging yield, we estimate InFO (or FOWLP in general) will incur just 5-10% higher cost over the flip chip package. However, low packaging yield results in high cost from die loss, which has kept the technology from mass adoption so far. Though there are still execution risks from now to 3Q16, apparently TSMC is making progress and likely can overcome the yield challenge. This is further supported by the recent announcement of Ultratech (an equipment vendor) which we believe just received a major order for TSMC’s InFO capacity build-up.

What that means is higher performance in the same thermal envelope. That means Apple would have to be willing for the SoC to consume more power, which means less battery life or a bigger battery.

Also, if the A9 was indeed of TSMC's 16FF, then the move to 16FF+ would have a few small performance benefits on its own, similar to Samsung's own 14LPP ('http://www.samsung.com/semiconductor/foundry/process-technology/14nm/') (10%).

This post ('https://www.macrumors.com/2015/11/06/tsmc-a10-production-info-wlp/') goes into InFO in more detail.

edit: one last note- they talk about removing the substrate. That would be the substrate above the die between the memory and application processor. You still need the interface between the die and board, which is a substrate. With InFO WLP, you just route all your dies on that one piece. To have no substrate would be chip-on-board, which isn't possible because board vendors can't make boards with the extremely fine pitches that logic die bumps have. That's why vendors are starting to introduce actual passive silicon wafers (interposers) into the process to get really dense routing to greater I/O to memory and other devices.